1. Field of the Invention
The present invention is related to a display device, and more particularly, to a display device with a uniform loading effect.
2. Description of the Prior Art
A display device (e.g. a liquid crystal display, LCD), includes conducting wires such as gate lines, common lines, data lines, or electrode structures such as pixel electrodes. In terms of circuit layout, whether design driven or due to other inevitable factors, signal interferences occur when the conducting wires are embedded too close to each other, causing a loading effect. When the loading effect does not distribute uniformly throughout each pixel, influences on each pixel may vary; such that an uneven loading effect may severely affect the quality of the display. Therefore, in designing the display device, uneven loading effects should be strongly avoided.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional display device. As shown in FIG. 1, the conventional display device 10 includes a substrate 12, which includes a display region 12D, a peripheral region 12P, and a chip bonding region 12C. The display device 10 includes a plurality of gate lines 14 and a plurality of data lines 16, disposed at the display region 12D of the substrate 12, wherein the gate lines 14 are perpendicular to the data lines 16, and two adjacent gate lines 14 and two adjacent data lines 16 define a pixel (sub-pixel). The peripheral region 12P of the display device 10 has a chip driver 20 disposed thereon. Each data line 16 has one end extending from the display region 12D to the chip bonding region 12C and electrically connected to the chip driver 20 in order to receive data signals. In contrast, each gate line 14 has one end extending from the display region 12D to the peripheral region 12P and electrically connected to the chip driver 20 disposed in the chip bonding region 12C through a conducting wire 18. Through the conducting wire 18, gate signals from the chip driver 20 are delivered to corresponding gate lines 14.
According to FIG. 1, the gate lines 14 of the display device 10 in the prior art are electrically connected to the chip driver 20 through the conducting wires 18 at the peripheral region 12P; however, due to different loading effects of the conducting wires 18 at the peripheral region 12P, and the scan lines 14 and the data lines 16 at the display region 12D, the display quality of the display device 10 is affected. Furthermore, in order to dispose the conducting wires 18, the display device 10 in the prior art must possess a larger peripheral region 12P, thus a narrow frame design cannot be achieved in this case.